1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.
2. Description of Related Art
Among nonvolatile semiconductor memory devices capable of programming/erasing electrically, a split gate type memory cell structure, a control gate of which is formed above a side wall of a word gate via a insulating film, as represented by the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure is known. The word gate and the control gate are typically made of poly silicon, so each surface is alloyed (silicided) to reduce wiring resistance substantively for improving conductivity.
In the split gate type MONOS memory having such configuration, the word gate and the control gate are insulated from each other via an only thin ONO (Oxide Nitride Oxide) film. Therefore, a silicide formed on the surface of the word gate and a silicide formed on the surface of the control gate short, thereby often causing a silicide short.
Thus, if the silicide short is occurred in the early stages, there is a problem that a yield is lowered by an initial failure. Further, if the separation of silicides is insufficient even if the silicide short is not occurred in the early stages, a short failure is occurred by applying a bias repeatedly in program/erase cycles, so there is a problem with reliability.
With respect to these problems, Japanese Unexamined Patent Application Publication No. 2002-231839 (Ogura et al.) discloses a technique to prevent the silicide short between the control gate and the word gate by forming the control gate with lower height than the word gate. Ogura et al. discloses that the height of the word gate is 2000 to 2500 Å and the height of the control gate is 1000 to 1250 Å.